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Version 1.1
28 Jul 2019
Aliases: nvmlEventTypeAll(3), nvmlEventTypeAll(3), nvmlEventTypeClock(3), nvmlEventTypeClock(3), nvmlEventTypeDoubleBitEccError(3), nvmlEventTypeDoubleBitEccError(3), nvmlEventTypeNone(3), nvmlEventTypeNone(3), nvmlEventTypePState(3), nvmlEventTypePState(3), nvmlEventTypeSingleBitEccError(3), nvmlEventTypeSingleBitEccError(3), nvmlEventTypeXidCriticalError(3), nvmlEventTypeXidCriticalError(3)


NVIDIA CUDA development files


NVIDIA's GPU programming toolkit


Event Types -


#define nvmlEventTypeSingleBitEccError 0x0000000000000001LL
Event about single bit ECC errors. #define nvmlEventTypeDoubleBitEccError 0x0000000000000002LL
Event about double bit ECC errors. #define nvmlEventTypePState 0x0000000000000004LL
Event about PState changes. #define nvmlEventTypeXidCriticalError 0x0000000000000008LL
Event that Xid critical error occurred. #define nvmlEventTypeClock 0x0000000000000010LL
Event about clock changes. #define nvmlEventTypeNone 0x0000000000000000LL
Mask with no events. #define nvmlEventTypeAll
Mask of all events.

Detailed Description

Event Types which user can be notified about. See description of particular functions for details.
See nvmlDeviceRegisterEvents and nvmlDeviceGetSupportedEventTypes to check which devices support each event.
Types can be combined with bitwise or operator ’|’ when passed to nvmlDeviceRegisterEvents

Define Documentation

#define nvmlEventTypeClock 0x0000000000000010LL

Kepler only

#define nvmlEventTypeDoubleBitEccError 0x0000000000000002LL

An uncorrected texture memory error is not an ECC error, so it does not generate a double bit event

#define nvmlEventTypePState 0x0000000000000004LL

On Fermi architecture PState changes are also an indicator that GPU is throttling down due to no work being executed on the GPU, power capping or thermal capping. In a typical situation, Fermi-based GPU should stay in P0 for the duration of the execution of the compute process.

#define nvmlEventTypeSingleBitEccError 0x0000000000000001LL

A corrected texture memory error is not an ECC error, so it does not generate a single bit event


Generated automatically by Doxygen for NVML from the source code.
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